1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly relates to a method of manufacturing a semiconductor device, which improves characteristics by allowing sufficient hydrogen to reach a substrate surface in hydrogen annealing treatment.
2. Description of the Related Art
With reference to FIGS. 11 to 13, description will be given of a conventional semiconductor device by taking an n-channel MOSFET having a trench structure as an example.
First, FIG. 11 shows a structure of a MOSFET 40. An n− type epitaxial layer 22 is laminated on an n+ type silicon semiconductor substrate 21 to provide a drain region, and a p-type channel layer 24 is provided thereon.
Trenches 27 are provided, which penetrate the channel layer 24 and reach the drain region 22. Inner walls of the trenches 27 are covered with a gate oxide film 31, and the trenches 27 are filled with polysilicon to form gate electrodes 33. In a surface of the channel layer 24 adjacent to the trenches 27, n+ type source regions 35 are formed. Moreover, in the surface of the channel layer 24 between the source regions 35 of two adjacent cells, p+ type body regions 34 are provided. Furthermore, when a gate voltage is applied to the gate electrodes 33, channel regions (not shown) are formed along the trenches 27 from the source regions 35. The gate electrodes 33 are covered with an interlayer insulating film 36. Thereafter, a barrier metal layer 37 is formed, which comes into contact with the source regions 35 and the body regions 34. Subsequently, a wiring layer 38 made of an aluminum alloy or the like, and a passivation film 41 are provided.
Next, description will be given of a conventional method of manufacturing a semiconductor device.
As shown in FIG. 12, the drain region 22 is formed by laminating an n− type epitaxial layer on the n+ type silicon semiconductor substrate 21. After an oxide film (not shown) is formed on a surface of the drain region 22, the oxide film in a portion of a channel layer is etched. By using this oxide film as a mask, boron is implanted over the entire surface of the resultant structure. Thereafter, boron is diffused to form the p-type channel layer 24.
Next, trenches are formed. By use of a CVD method, a CVD oxide film of NSG (Non-doped Silicate Glass) is formed on the entire surface of the resultant structure. Thereafter, a mask made of a resist film is provided thereon except portions of the CVD oxide film where the openings of the trenches are to be formed. Subsequently, the CVD oxide film is dry-etched to be partially removed. Thus, trench openings are formed, in which the channel layer 24 is exposed.
Furthermore, by using the CVD oxide film as a mask, the epitaxial layer 22 exposed from the trench opening is dry-etched with CF gas and HBr gas. Thus, the trench 27 is formed, which penetrates the channel layer 24 and reaches the drain region 22.
Thereafter, by performing dummy oxidation, a dummy oxide film (not shown) is formed on inner walls of the trenches 27 and on a surface of the channel layer 24. Accordingly, an etching damage in dry etching is eliminated. Thereafter, the dummy oxide film formed by the dummy oxidation and the CVD oxide film are simultaneously removed by use of an oxide film etchant such as hydrofluoric acid. Thus, a stable gate oxide film can be formed. Moreover, by performing thermal oxidation at a high temperature, the openings of the trenches 27 are made round. Accordingly, there is also achieved an effect of preventing field concentration in the openings of the trenches 27. Thereafter, a gate oxide film 31 is formed. Specifically, by thermally oxidizing the entire surface of the resultant structure, the gate oxide film 31 is formed to have a thickness of about several hundred Å, for example, according to a threshold thereof.
Subsequently, a non-doped polysilicon layer is deposited on the entire surface of the resultant structure, and high concentration of phosphorus is implanted and diffused to achieve a high conductivity. The polysilicon layer deposited on the entire surface of the resultant structure is dry-etched without using a mask to leave gate electrodes 33 buried in the trenches 27.
Next, as shown in FIG. 13, the body regions 34 for stabilizing a potential of the substrate, and the source regions 35 are formed. First, boron ions are selectively implanted by using a mask made of a resist film, and then the resist film is removed. Moreover, a new resist film is deposited so as to expose the predetermined source regions 35 and gate electrodes 33. Thereafter, ion implantation of arsenic is performed to remove the resist film. Subsequently, a BPSG (Boron Phosphorus Silicate Glass) layer is deposited on the entire surface of the resultant structure by use of the CVD method, and impurities are diffused. Thus, the body regions 34 and the source regions 35 are formed. Thereafter, the BPSG layer is etched by use of a resist film as a mask, and the interlayer insulating film 36 is left at least on the gate electrodes 33.
Furthermore, in order to form a wiring layer as shown in FIG. 11, the barrier metal layer 37 is first provided. Specifically, the barrier metal layer 37 is formed by sputtering Ti/TiN or the like on the entire surface of the resultant structure. Subsequently, an aluminum alloy to be the wiring layer 38 is sputtered on the entire surface of the resultant structure. Thereafter, heat treatment is performed in order to stabilize the metal and the silicon surface. This heat treatment is performed for about 30 minute s at a temperature of 300 to 500° C. (for example, about 400° C.), which is below a melting point of the aluminum alloy, in hydrogen-containing gas. Subsequently, for surface protection, a passivation film made of SiN or the like is formed. Furthermore, in order to eliminate a damage, heat treatment is performed for about 30 minutes at 300 to 500° C. (for example, 400° C.). Thus, the final structure shown in FIG. 11 is obtained. This technology is described for instance in Japanese Patent Application Publication No. Hei 8-37236.
As described above, as a wiring used for a semiconductor device including a silicon substrate, an aluminum-based metal material, such as an aluminum alloy, is generally used. Moreover, it is required to perform heat treatment to achieve an ohmic characteristic in an interface between Al (aluminum) and a Si (silicon) substrate.
However, because of a high diffusion rate of Si in Al, Al and Si are diffused to cause a phenomenon called a spike which destroys a pn junction. In order to prevent this phenomenon, Si is previously contained in Al.
If Si is contained in Al, Si contained in Al is diffused and undergoes grain growth by heat treatment. Accordingly, a Si nodule may be deposited on a contact interface with the substrate. This Si nodule becomes a factor that causes a contact failure by blocking a contact region between a body region, that is a minute region, and a wiring layer. Moreover, since the Si nodule itself has a high resistance, the Si nodule becomes a factor that causes an unstable contact resistance or increases a contact resistance.
In order to prevent the problems described above, a barrier metal layer made of titanium-based metal is formed before the wiring layer (Al) is formed.
Furthermore, due to oxidation performed in an element region formation step, and the like, a dangling bond in which a Si bonding hand is cut off may exist in a surface of the substrate. In this case, the surface is considered to be negatively charged. In other words, due to a potential generated, the substrate is set in the same state as where an electric field is applied to the surface thereof Accordingly, there occurs a variation in a threshold voltage.
Thus, in the conventional MOSFET described above, after formation of an element region, the barrier metal layer 37 and the wiring layer 38 are sequentially formed in a wiring layer formation step. Thereafter, heat treatment is performed in hydrogen-containing gas.
Specifically, heat treatment for achieving the ohmic characteristic in the interface between Al and the silicon substrate is performed in the hydrogen-containing gas. Accordingly, hydrogen is allowed to reach the substrate interface and the like, and silicon which has lost relation with each other and hydrogen are bonded. Thus, charges on the substrate interface can be removed. Therefore, improvement in characteristics (for example, a reduction in a dark current) and stability in characteristics (for example, stability in a threshold voltage VGSOFF) can be achieved.
However, depending on a kind of a barrier, a desired threshold voltage VGSOFF may not be obtained even if heat treatment in a hydrogen-containing gas atmosphere (hereinafter referred to as hydrogen annealing) is performed.
Accordingly, the following is considered as a cause of a shift in the threshold voltage VGSOFF. Specifically, since the titanium-based metal, that is the barrier metal layer, has a hydrogen occlusion property, hydrogen is occluded by the barrier metal layer before reaching an interface between the semiconductor substrate and the gate oxide film in a hydrogen annealing step. Thus, an amount of hydrogen which contributes to elimination of charges generated on the Si interface is reduced.
As an example, in an n-channel MOSFET having a trench structure, since a threshold voltage VGSOFF is shifted down (the threshold voltage drops), it is required to increase a concentration of impurities implanted into a channel layer, in order to obtain a desired threshold. Thus, there is a problem that an on-resistance is increased.
Specifically, in the conventional method, there is a problem that a substantial effect of hydrogen annealing treatment for removing charges of the substrate is not obtained due to the barrier metal layer which prevents the spike and avoids the contact failure caused by the Si nodule.